1. Field of the Invention
The present invention relates to semiconductor chip packaging, and, in particular, to stacked multiple chip packages.
2. Discussion of the Related Art
Semiconductor die or chip packages are used to protect the semiconductor device (e.g., an integrated circuit chip) and allow the chip to be electrically connected to external circuitry. The chip typically has a surface containing active circuit elements that can be accessed via conductors on the chip, such as bonding pads. The chip can be packaged using numerous packaging techniques, as is known in the art. A typical method includes the following sequence of steps:
1. Attach the chip to a package, such as by depositing die attach epoxy on the chip pad of a lead frame contained within a lead frame tape, compressing the chip into the epoxy and lead frame, and curing the epoxy;
2. Attach bond wires between the bonding pads on the chip and lead fingers on the lead frame;
3. Place the lead frame tape within a mold, and inject a plastic packaging compound into the mold to encapsulate the chip and a portion of the lead frame;
4. Separate the leads from the lead frame tape; and
5. Trim and form the leads.
The package can then be placed into a printed circuit board to access the circuitry on the IC chip.
Due to size limitations of the printed circuit board (PCB), only a finite number of packaged chips can be placed on the PCB. As the complexity of applications increases, a greater number of chips are needed on the PCB to implement the necessary functions, which would require larger size PCBs. However, it is also desirable to decrease the size of PCBs and devices containing PCBs. One method of achieving both these objectives is to increase the number of chips in a package, such as by stacking the chips, without increasing the planar area of the package. For example, an adhesive insulative film layer secures the upper surface of a first chip to the lower surface of a lead frame, where the upper surface of the first chip contains bond pads. An adhesive insulative film layer also secures the lower surface of a second chip to the upper surface of the lead frame, where the second chip is smaller than the first chip. The bond pads for both chips are interconnected via bond wires and connected to leads on the lead frame. One disadvantage to this method is that the same size chip cannot be used.
Accordingly, it is desirable to package multiple same size chips, while minimizing the size of the package.
In accordance with the present invention, a chip or die package and method of forming the package are disclosed that allows multiple same-sized dice or chips to be stacked in a single package. In one embodiment, two or more chips with center bond pads are secured to a substrate sheet or strip. Bond wires emanating from the center bond pads extend down through the substrate and are connected to a metallization layer. Solder balls or other conductive means are in contact with a portion of the metallization layer underneath one chip. All other chip or chips are xe2x80x9cfoldedxe2x80x9d on top of the one chip, resulting in a package of chips, with each chip stacked upon another. Each chip is separated from another by at least an insulative spacer.
In another embodiment, two chips are formed on opposite sides of a flexible substrate at different portions of the substrate. Bond wires from both chips extend through the substrate to connect each chip with an opposite metallization layer. Solder balls or other conductive means are formed on the metallization layer opposite one chip. The substrate is then bent away from the solder balls until the chips are coupled via an adhesive spacer and a portion of the substrate. The two chips, which can be the same size, approximately overlie each other in the resulting package.